A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay

An 800MS/s CT ∆Σ ADC with 16MHz/32MHz bandwidths consumes 47.6mW from 1.8V and occupies 1mm in a 0.18μm CMOS process. The DR/SNR/SNDR for the two bandwidths are 75/67/65 dB and 64/57/57 dB respectively. Excess loop delay (ELD) of more than one cycle is compensated using a fast path outside the flash ADC. This and a low latency flash ADC and delay free DAC calibration result in the highest reported sampling rate in this process. I. MOTIVATION The sampling period Ts (= 1/ fs) of a continuous time ∆Σ modulator (CTDSM) has to be larger than the delay of the shortest loop. Consequently the sampling rate and signal bandwidth for a given signal to noise ratio (SNR) are limited. CTDSMs consist of a loop filter, flash ADC, and a DAC in a feedback loop. Each of these components contributes to excess loop delay (ELD). ELD, if uncompensated, causes peaking in the noise transfer function (NTF) or instability of the loop. To prevent this, ELD compensation techniques[1] are employed. These usually entail using a shorter feedback path around the flash ADC. This is illustrated in the block diagram of a cascade of integrator feedforward (CIFF) ∆Σ modulator with conventional ELD compensation (Fig. 1), where the path with gain k0 mitigates ELD. The shorter path k0 can be implemented in various ways: e.g. an additional DAC[1], [2], perhaps bypassing the DEM or using a differentiating path inside the loop filter. Regardless of the method, the shortest loop delay is at least equal to the delay of the flash ADC. In a given process there is a lower limit τADC,min on the delay of the flash ADC. For realizing stable lowpass ∆Σ modulators with high signal to quantization noise ratio (SQNR), Ts has to be larger than τADC,min. As Ts approaches τADC,min, the required value of k0 becomes very large and realizing this gain with a small delay becomes impossible. Therefore, in practice, the lowest value of Ts is restricted to about 2τADC,min and k0 is used to compensate for Ts/2 = τADC,min [2], [3]. Attempting to use the method in Fig. 1 to realize lowpass CTDSMs with higher sampling rates where ELD> Ts while keeping the modulator stable results in severe degradation of SQNR [4], [5]. This is a fundamental property of stable minimum phase loops with ELD > Ts and one cannot workaround it by altering k0 or the coefficients of the loop filter [4]. To increase the sampling rates well beyond this limit and consequently extend the signal bandwidths, ADC delays The authors are with the Department of Electrical Engineering, Indian Institute of Technology, Madras, Chennai 600036, India. E-mail: [email protected]; This work was supported in part by the Ministry of Information Technology, Government of India. Loop filter L(s) ADC